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d a t a sh eet product speci?cation supersedes data of 1996 oct 25 file under integrated circuits, ic12 1997 apr 07 integrated circuits pcf2116 family lcd controller/drivers
1997 apr 07 2 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family contents 1 features 2 applications 3 general description 3.1 packages 4 ordering information 5 block diagram 6 pinning 7 pin functions 7.1 rs: register select (parallel control) 7.2 r/w: read/write (parallel control) 7.3 e: data bus clock 7.4 db0 to db7: data bus 7.5 c1 to c60: column driver outputs 7.6 r1 to r32: row driver outputs 7.7 vlcd: lcd power supply 7.8 v0: vlcd control input 7.9 osc: oscillator 7.10 scl: serial clock line 7.11 sda: serial data line 7.12 sa0: address pin 7.13 t1: test pad 8 functional description 8.1 lcd supply voltage generator, pcf2114x and pcf2116x 8.2 lcd supply voltage generator, pcf2116k 8.3 character generator rom (cgrom) 8.4 lcd bias voltage generator 8.5 oscillator 8.6 external clock 8.7 power-on reset 8.8 registers 8.9 busy flag 8.10 address counter (ac) 8.11 display data ram (ddram) 8.12 character generator rom (cgrom) 8.13 character generator ram (cgram) 8.14 cursor control circuit 8.15 timing generator 8.16 lcd row and column drivers 8.17 programming mux 1 : 16 displays with the pcf2114x 8.18 programming mux 1 : 32 displays with the pcf2114x 8.19 reset function 9 instructions 9.1 clear display 9.2 return home 9.3 entry mode set 9.4 display on/off control 9.5 cursor/display shift 9.6 function set 9.7 set cgram address 9.8 set ddram address 9.9 read busy flag and address 9.10 write data to cgram or ddram 9.11 read data from cgram or ddram 10 interface to microcontroller (parallel interface) 11 interface to microcontroller (i 2 c-bus interface) 11.1 characteristics of the i 2 c-bus 11.2 bit transfer 11.3 start and stop conditions 11.4 system configuration 11.5 acknowledge 11.6 i 2 c-bus protocol 12 limiting values 13 handling 14 dc characteristics 15 dc characteristics (pcf2116k) 16 ac characteristics 17 timing characteristics 18 application information 18.1 8-bit operation, 1-line display using internal reset 18.2 4-bit operation, 1-line display using internal reset 18.3 8-bit operation, 2-line display 18.4 i 2 c operation, 1-line display 18.5 initializing by instruction 19 bonding pad locations 20 package outline 21 soldering 22 definitions 23 life support applications 24 purchase of philips i 2 c components
1997 apr 07 3 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 1 features single chip lcd controller/driver 1 or 2-line display of up to 24 characters per line, or 2 or 4 lines of up to 12 characters per line 5 7 character format plus cursor; 5 8 for kana (japanese syllabary) and user defined symbols on-chip: C generation of lcd supply voltage (external supply also possible) C generation of intermediate lcd bias voltages C oscillator requires no external components (external clock also possible) display data ram: 80 characters character generator rom: 240 characters character generator ram: 16 characters 4 or 8-bit parallel bus or 2-wire i 2 c-bus interface cmos/ttl compatible 32 row, 60 column outputs mux rates 1 : 32 and 1 : 16 uses common 11 code instruction set logic supply voltage range, v dd - v ss : 2.5 to 6 v display supply voltage range, v dd - v lcd : 3.5 to 9 v low power consumption i 2 c-bus address: 011101 sa0. 2 applications telecom equipment portable instruments point-of-sale terminals. 3 general description the pcf2116 family of lcd controller/drivers consists of the pcf2116x, the pcf2114x and the pcf2116k. the term pcf2116 is used to refer to all devices for common information. specific information is given in separate paragraphs. the x in pcf2116x and pcf2114x represents a specific letter code for a character set in the character generator rom (cgrom). the different character sets currently available are specified by the letters a, c, and g (see figs 8 to 10). other character sets are available on request. the pcf2116 is a low-power cmos lcd controller and driver, designed to drive a split screen dot matrix lcd display of 1 or 2 lines by 24 characters or 2 or 4 lines by 12 characters with 5 8 dot format. all necessary functions for the display are provided in a single chip, including on-chip generation of lcd bias voltages, resulting in a minimum of external components and lower system power consumption. the chip contains a character generator and displays alphanumeric and kana (japanese) characters. the pcf2116 interfaces to most microcontrollers via a 4 or 8-bit bus or via the 2-wire i 2 c-bus. to allow partial v dd shutdown the esd protection system of the scl and sda pins does not use a diode connected to v dd . the pcf2116k differs from the other members of the family in that: v lcd /v op generation is different (see section 8.1) it is available with character set c only (see fig.9). 4 ordering information note 1. the letter x in the type number represents the letter of the required built-in character set: a, c or g. type number (1) package name description version pcf2116xu/10 - chip on flexible film carrier - pcf2114xu/10 - chip on flexible film carrier - pcf2116xu/12 - chip with bumps on flexible film carrier - pcf2114xu/12 - chip with bumps on flexible film carrier - pcf2116xhz lqfp128 plastic low profile quad flat package; 128 leads; body 14 20 1.4 mm sot425-1
1997 apr 07 4 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 5 block diagram fig.1 block diagram (pin numbers for lqfp128 package). h andbook, full pagewidth shift register 32-bit mga797 - 1 v ss v dd character generator ram (cgram) 16 characters character generator rom (cgrom) 240 characters cursor + data control 5 5 shift register 5 x 12-bit 60 data latches 60 column drivers 6 bias voltage generator v lcd generator 93, 95, 97 60 32 row drivers 8 display data ram (ddram) 80 characters 32 84 to 77, 115 to 122 76 to 69, 123 to 128, 1 and 4 address counter (ac) instruction decoder instruction register (ir) data register (dr) busy flag 7 8 8 i/o buffer 8 7 7 8 92 104, 106 109, 112 v lcd display address counter power - on reset timing generator oscillator 7 102 osc c1 to c60 r1 to r32 4 105, 103, 98, 96 4 108 110 113 db0 to db3 db4 to db7 e rs r/w v 0 pcf2116 88 scl 90 sda 107 sa0 111 t1 94, 91, 89, 87 68, 65 to 38 35 to 5
1997 apr 07 5 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 6 pinning symbol lqfp128 ffc pad type description r31 1 27 o lcd row driver output n.c. 2 and 3 -- not connected r32 4 28 o lcd row driver output c60 to c30 5 to 35 29 to 59 o lcd column driver outputs 60 to 30 n.c. 36 and 37 -- not connected c29 to c2 38 to 65 60 to 87 o lcd column driver outputs 29 to 2 n.c. 66 and 67 -- not connected c1 68 88 o lcd column driver output 1 r24 to r17 69 to 76 89 to 96 o lcd row driver outputs r8 to r1 77 to 84 97 to 104 o lcd row driver outputs n.c. 85 and 86 -- not connected db7 87 105 i/o 1 bit of 8-bit bidirectional data bus scl 88 106 i i 2 c-bus serial clock input db6 89 107 i/o 1 bit of 8-bit bidirectional data bus sda 90 108 i/o i 2 c-bus serial data input/output db5 91 109 i/o 1 bit of 8-bit bidirectional data bus v 0 92 110 i control input for v lcd v lcd1 93 111 i/o lcd supply voltage input/output 1 db4 94 112 i/o 1 bit of 8-bit bidirectional data bus v lcd2 95 113 i/o lcd supply voltage input/output 2 db3 96 114 i/o 1 bit of 8-bit bidirectional data bus v lcd3 97 115 i/o lcd supply voltage input/output 3 db2 98 116 i/o 1 bit of 8-bit bidirectional data bus n.c. 99 to 101 -- not connected osc 102 1 i oscillator/external clock input db1 103 2 i/o 1 bit of 8-bit bidirectional data bus v dd2 104 3 p supply voltage 2 db0 105 4 i/o 1 bit of 8-bit bidirectional data bus v dd1 106 5 p supply voltage 1 sa0 107 6 i i 2 c-bus address pin e 108 7 i data bus clock input (parallel control) v ss1 109 8 p ground (logic) 1 r/ w 110 9 i read/write input (parallel control) t1 111 10 i test pad (connect to v ss ) v ss2 112 11 p ground (logic) 2 rs 113 12 i register select input (parallel control) n.c. 114 -- not connected r9 to r16 115 to 122 13 to 20 o lcd row driver outputs r25 to r30 123 to 128 21 to 26 o lcd row driver outputs
1997 apr 07 6 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family fig.2 pin configuration (lqfp128). handbook, full pagewidth mbd451 - 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 31 32 33 34 35 36 37 38 72 71 70 69 68 67 66 65 pcf2116 r31 n.c. n.c. r32 c60 c59 c58 c57 c56 c55 c54 c53 c52 c51 c50 c49 c48 c47 c46 c45 c44 c43 c42 c41 c40 c39 c38 c37 c36 c35 c34 c33 c32 c31 c30 n.c. n.c. c29 osc n.c. n.c. n.c. db2 v db3 db4 v db5 sda db6 scl db7 n.c. n.c. r1 r2 r3 r4 r5 r6 r7 r8 r17 r18 r19 r20 r21 r22 r23 r24 c1 n.c. n.c. c2 lcd3 v lcd2 v lcd1 0 c28 c27 c26 c25 c24 c23 c22 c21 c20 c19 c18 c17 c16 c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 r30 r29 r28 r27 r26 r25 r16 r15 r14 r13 r12 r11 r10 r9 n.c. rs t1 r/w e sa0 db0 v db1 dd2 v dd1 v ss1 v ss2
1997 apr 07 7 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 7 pin functions 7.1 rs: register select (parallel control) rs selects the register to be accessed for read and write when the device is controlled by the parallel interface. rs = logic 0 selects the instruction register for write and the busy flag and address counter for read. rs = logic 1 selects the data register for both read and write. there is an internal pull-up on pin rs. 7.2 r/ w : read/write (parallel control) r/ w selects either the read (r/ w = logic 1) or write (r/ w = logic 0) operation when control is by the parallel interface. there is an internal pull-up on this pin. 7.3 e: data bus clock the e pin is set high to signal the start of a read or write operation when the device is controlled by the parallel interface. data is clocked in or out of the chip on the negative edge of the clock. note that this pin must be tied to logic 0 (v ss ) when i 2 c-bus control is used. 7.4 db0 to db7: data bus the bidirectional, 3-state data bus transfers data between the system controller and the pcf2116. db7 may be used as the busy flag, signalling that internal operations are not yet completed. in 4-bit operations the 4 higher order lines db4 to db7 are used; db0 to db3 must be left open circuit. there is an internal pull-up on each of the data lines. note that these pins must be left open circuit when i 2 c-bus control is used. 7.5 c1 to c60: column driver outputs these pins output the data for pairs of columns. this arrangement permits optimized chip-on-glass (cog) layout for 4-line by 12 characters. 7.6 r1 to r32: row driver outputs these pins output the row select waveforms to the left and right halves of the display. 7.7 v lcd : lcd power supply negative power supply for the liquid crystal display. this may be generated on-chip or supplied externally. 7.8 v 0 : v lcd control input the input level at this pin determines the generated v lcd output voltage. 7.9 osc: oscillator when the on-chip oscillator is used this pin must be connected to v dd . an external clock signal, if used, is input at this pin. 7.10 scl: serial clock line input for the i 2 c-bus clock signal. 7.11 sda: serial data line input/output for the i 2 c-bus data line. 7.12 sa0: address pin the hardware sub-address line is used to program the device sub-address for 2 different pcf2116s on the same i 2 c-bus. 7.13 t1: test pad must be connected to v ss . not user accessible. 8 functional description (see fig.1) 8.1 lcd supply voltage generator, pcf2114x and pcf2116x the on-chip voltage generator is controlled by bit g of the function set instruction and v 0 . v 0 is a high-impedance input and draws no current from the system power supply. its range is between v ss and v dd - 1 v. when v 0 is connected to v dd the generator is switched off and an external voltage must be supplied to pin v lcd . this may be more negative than v ss . when g = logic 1 the generator produces a negative voltage at pin v lcd , controlled by the input voltage at pin v 0 . the lcd operating voltage is given by the relationship: v op = 1.8v dd - v 0 where: v op =v dd - v lcd v lcd =v 0 - (0.8v dd ) when g = logic 0, the generated output voltage v lcd is equal to v 0 (between v ss and v dd ). in this instance: v op =v dd - v 0 when v lcd is generated on-chip the v lcd pin should be decoupled to v dd with a suitable capacitor. v dd and v 0 must be selected to limit the maximum value of v op to 9 v. figure 3 shows the two generator control characteristics.
1997 apr 07 8 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 8.2 lcd supply voltage generator, pcf2116k in the pcf2116k version, v 0 is connected through an on-chip resistor (r 0 ) to v lcd . resistor r 0 has a nominal value of 1 m w and draws a typical current of 4 m a from the pin v 0 . a constant voltage (equal to 1.34v dd ) is always present across r 0 . the voltage range of the pcf2116k is between v ss and v dd - 0.5 v (see fig.4). when v 0 is connected to v dd the generator is switched off and an external voltage must be supplied to pin v lcd . this may be more negative than v ss . when g = logic 1 the generator produces a negative voltage at pin v lcd , controlled by the input voltage at pin v 0 . the lcd operating voltage is given by the relationship: v op = 2.34v dd - v 0 where: v op =v dd - v lcd v lcd =v 0 - (1.34v dd ) when g = logic 0, the generated output voltage v lcd is equal to v 0 (between v ss and v dd ). in this instance: v op =v dd - v 0 8.3 character generator rom (cgrom) the standard character sets a, c and g are available for the pcf2114x and pcf2116x. standard character set c is available for the pcf2116k. 8.4 lcd bias voltage generator the intermediate bias voltages for the lcd display are also generated on-chip. this removes the need for an external resistive bias chain and significantly reduces the system power consumption. the optimum levels depend on the multiplex rate and are selected automatically when the number of lines in the display is defined. the optimum value of v op depends on the multiplex rate, the lcd threshold voltage (v th ) and the number of bias levels and is given by the relationships in table 1.using a 5-level bias scheme for 1 : 16 mux rate allows v op <5v for most lcd liquids. the effect on the display contrast is negligible. 8.5 oscillator the on-chip oscillator provides the clock signal for the display system. no external components are required. pin osc must be connected to v dd . 8.6 external clock if an external clock is to be used, it must be input at pin osc. the resulting display frame frequency is given by f frame = 1 2304 f osc . a clock signal must always be present, otherwise the lcd may be frozen in a dc state. 8.7 power-on reset the power-on reset block initializes the chip after power-on or power failure. 8.8 registers the pcf2116 has two 8-bit registers, an instruction register (ir) and a data register (dr). the register select signal (rs) determines which register will be accessed. the instruction register stores instruction codes such as display clear and cursor shift, and address information for the display data ram (ddram) and character generator ram (cgram). the instruction register can be written to, but not read, by the system controller. the data register temporarily stores data to be read from the ddram and cgram. when reading, data from the ddram or cgram corresponding to the address in the address counter is written to the data register prior to being read by the read data instruction. 8.9 busy flag the busy flag indicates the free/busy status of the pcf2116. logic 1 indicates that the chip is busy and further instructions will not be accepted. the busy flag is output to pin db7 when rs = logic 0 and r/ w = logic 1. instructions should only be written after checking that the busy flag is logic 0 or waiting for the required number of clock cycles. table 1 optimum values for v op mux rate number of bias levels v op /v th discrimination v on /v off 1 : 16 5 3.67 1.277 1 : 32 6 5.19 1.196
1997 apr 07 9 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family fig.3 v op as a function of v 0 control characteristics. a. high-voltage mode v op = 1.8v dd - v 0 . b. buffer mode v op =v dd - v 0 . mga798 9 8 7 6 5 4 3.5 0123456 9 v 6 = v dd op(min) dd v = 0.8 x v 1 v 0 v op 5 4 3 2.5 op(max) dd v = 1.8 x v g = 1 mga799 9 8 7 6 5 4 3.5 0123456 6 = v dd v 0 v op 5 4 g = 0
1997 apr 07 10 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family fig.4 v op as a function of v 0 control characteristics (pcf2116k). a. high-voltage mode v op = 2.34v dd - v 0 . b. buffer mode v op =v dd - v 0 . mga799 9 8 7 6 5 4 3.5 0123456 6 = v dd v 0 v op 5 4 g = 0 mbh667 9 8 7 6 5 4 3.5 0123456 9 v 6 v 0 v op 5 4 = v dd 3 2.5 g = 1 v op(min) = 1.34 v dd + 0.5
1997 apr 07 11 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 8.10 address counter (ac) the address counter assigns addresses to the ddram and cgram for reading and writing and is set by the instructions set cgram address and set ddram address. after a read/write operation the address counter is automatically incremented or decremented by 1.the address counter contents are output to the bus (db0 to db6) when rs = logic 0 and r/ w = logic 1. 8.11 display data ram (ddram) the display data ram stores up to 80 characters of display data represented by 8-bit character codes. ram locations not used for storing display data can be used as general purpose ram. the basic ddram-to-display mapping scheme is shown in fig.5. with no display shift the characters represented by the codes in the first 12 or 24 ram locations starting at address 00 in line 1 are displayed. subsequent lines display data starting at addresses 20, 40, or 60 hex. figs 6 and 7 show the ddram-to-display mapping principle when the display is shifted. the address range for a 1-line display is 00 to 4f; for a 2-line display from 00 to 27 (line 1) and 40 to 67 (line 2); for a 4-line display from 00 to 13, 20 to 33, 40 to 53 and 60 to 73 for lines 1, 2, 3 and 4 respectively. for 2 and 4-line displays the end address of one line and the start address of the next line are not consecutive. when the display is shifted each line wraps around independently of the others (figs 6 and 7). when data is written into the ddram wrap-around occurs from 4f to 00 in 1-line mode and from 27 to 40 and 67 to 00 in 2-line mode; from 13 to 20, 33 to 40, 53 to 60 and 73 to 00 in 4-line mode. 8.12 character generator rom (cgrom) the character generator rom generates 240 character patterns in 5 8 dot format from 8-bit character codes. figures 8 to 10 show the character sets currently available. 8.13 character generator ram (cgram) up to 16 user-defined characters may be stored in the character generator ram. the cgrom and cgram use a common address space, of which the first column is reserved for the cgram (see fig.8). figure 11 shows the addressing principle for the cgram. 8.14 cursor control circuit the cursor control circuit generates the cursor (underline and/or character blink as shown in fig.12) at the ddram address contained in the address counter. when the address counter contains the cgram address the cursor will be inhibited. 8.15 timing generator the timing generator produces the various signals required to drive the internal circuitry. internal chip operation is not disturbed by operations on the data buses. 8.16 lcd row and column drivers the pcf2116 contains 32 row and 60 column drivers, which connect the appropriate lcd bias voltages in sequence to the display, in accordance with the data to be displayed. the bias voltages and the timing are selected automatically when the number of lines in the display is selected. figures 13 and 14 show typical waveforms. in 1-line mode (1 : 16) the row outputs are driven in pairs: r1/r17, r2/r18 for example. this allows the output pairs to be connected in parallel, providing greater drive capability. unused outputs should be left unconnected.
1997 apr 07 12 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family fig.5 ddram-to-display mapping; no shift. handbook, 4 columns 12345 222324 00 01 02 03 04 15 16 17 18 19 4c 4d 4e 4f non-displayed ddram addresses display position (decimal) ddram address (hex) 1-line display 64 65 66 67 40 41 42 43 44 55 56 57 58 59 00 01 02 03 04 15 16 17 18 19 24 25 26 27 non-displayed ddram address ddram (hex) address 2-line display line 1 line 2 mla792 handbook, 4 columns 123456789101112 non-displayed ddram addresses ddram address (hex) 4 line display 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 73 line 1 line 2 line 3 line 4 mla793
1997 apr 07 13 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family fig.6 ddram-to-display mappi7ng; right shift. 27 00 01 02 03 67 40 41 42 43 14 15 16 54 55 56 ddram address (hex) line 1 line 2 2-line display 1 2 3 4 5 22 23 24 4f 00 01 02 03 14 15 16 display position (decimal) ddram address (hex) 1-line display mla802 13 01 02 03 04 05 06 07 08 09 0a 20 21 22 23 24 25 26 27 28 29 2a 33 40 41 42 43 44 45 46 47 48 49 4a 53 60 61 62 63 64 65 66 67 68 69 6a 73 123456789101112 ddram address (hex) line 1 line 2 line 3 line 4 4-line display 00 mla803 fig.7 ddram-to-display mapping; left shift. 1 2 3 4 5 22 23 24 05 01 02 03 04 16 17 18 41 42 43 44 45 56 57 58 05 01 02 03 04 16 17 18 display position (decimal) ddram address (hex) ddram address (hex) line 1 line 2 1-line display 2-line display mla815 01 02 03 04 05 06 07 08 09 0a 0b 0c 21 22 23 24 25 26 27 28 29 2a 2b 2c 41 42 43 44 45 46 47 48 49 4a 4b 4c 61 62 63 64 65 66 67 68 69 6a 6b 6c 123456789101112 ddram address (hex) line 1 line 2 line 3 line 4 4-line display mla816
1997 apr 07 14 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family fig.8 character set a in cgrom: pcf2116a; pcf2114a. handbook, full pagewidth mlb245 - 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 upper 4 bits lower 6 bits xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110 xxxx 1111 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1997 apr 07 15 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family fig.9 character set c in cgrom: pcf2116c; pcf2114c . handbook, full pagewidth mlb895 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 upper 4 bits lower 4 bits xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110 xxxx 1111 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 cg ram 1
1997 apr 07 16 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family fig.10 character set g in cgrom: pcf2116g; pcf2114g . handbook, full pagewidth mlb896 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 upper 4 bits lower 6 bits xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110 xxxx 1111 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 cg ram 1
1997 apr 07 17 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family fig.11 relationship between cgram addresses and data and display patterns. handbook, full pagewidth mga800 - 1 76543210 6543210 43210 higher order bits lower order bits lower order bits higher order bits lower order bits higher order bits 00000000 0000000 0 001 000 010 000 011 0 100 0 00 101 00 0 110 000 111 00000 000 000 001 0 0 0 010 00 00 011 100 101 00 00 110 00 00 111 00000 001 00000001 0001 00000010 00001111 00001111 00001111 00001111 01 0 0000 100 101 110 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111 character codes (ddram data) cgram address character patterns (cgram data) character pattern example 1 cursor position character pattern example 2 character code bits 0 to 3 correspond to cgram address bits 3 to 6. cgram address bits 0 to 2 designate character pattern line position. the 8th line is the cursor position and display is performed by logical or with the cursor. data in the 8th line will appear in the cursor position. character pattern column positions correspond to cgram data bits 0 to 4, as shown in fig.11 (bit 4 being at the left end). as shown in figs 8 and 11, cgram character patterns are selected when character code bits 4 to 7 are all logic 0. cgram data = logic 1 corresponds to selection for display. only bits 0 to 5 of the cgram address are set by the set cgram address instruction. bit 6 can be set using the set ddram address instruction or by using the auto-increment feature during cgram write. all bits 0 to 6 can be read using the read busy flag and address inst ruction.
1997 apr 07 18 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family fig.12 cursor and blink display examples. mga801 cursor 5 x 7 dot character font alternating display cursor display example blink display example
1997 apr 07 19 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family fig.13 typical lcd waveforms; 1-line mode. handbook, full pagewidth mga802 - 1 v dd v 2 v v 5 lcd row 1 col 1 state 1 (on) state 2 (on) 0.25 v op 0 v state 1 1-line display (1:16) frame n 1 frame n row 9 row 2 col 2 state 2 123 16123 16 34 v /v v dd v 2 v v 5 lcd 34 v /v v dd v 2 v v 5 lcd 34 v /v v dd v 2 v v 5 lcd 34 v /v v dd v 2 v v 5 lcd 3 4 v /v 0.25 v op 0.25 v op 0 v 0.25 v op v op v op v op v op
1997 apr 07 20 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family fig.14 typical lcd waveforms; 2-line mode. handbook, full pagewidth mga803 - 1 v dd v 2 v v v v 3 4 5 lcd row 1 v dd v 2 v v v v 3 4 5 lcd v dd v 2 v v v v 3 4 5 lcd col 1 v dd v 2 v v v v 3 4 5 lcd state 1 (on) state 2 (on) 0.15 v op 0 v v op v op v op state 1 2-line display (1:32) frame n 1 frame n row 9 row 2 col 2 v dd v 2 v v v v 3 4 5 lcd 0.15 v op 0.15 v op 0 v 0.15 v op v op state 2 123 3212 3 32
1997 apr 07 21 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 8.17 programming mux 1 : 16 displays with the pcf2114x the pcf2114x can be used in: 1-line mode to drive a 2-line display 2 12 characters with mux rate 1 : 16, resulting in better contrast. the internal data flow of the chip is optimized for this purpose. with the function set instruction m and n are set to 0, 0. figures 15 to 17 show ddram addresses of the display characters. the second row of each table corresponds to either the right half of a 1-line display or to the second line of a 2-line display. wrap around of data during display shift or when writing data is non-standard. fig.15 ddram-to-display mapping; no shift (pcf2114x). h andbook, full pagewidth 00 01 02 03 04 05 06 07 08 09 0a 0b 1 23 4 5 67 8 9 10 11 12 mlb899 display position ddram address 0c 0d 0e 0f 10 11 12 13 14 15 16 17 13 14 15 16 17 18 19 20 21 22 23 24 display position ddram address fig.16 ddram-to-display mapping; right shift (pcf2114x). h andbook, full pagewidth 4f 00 01 02 03 04 05 06 07 08 09 0a 1 23 4 5 67 8 9 10 11 12 mlb900 display position ddram address 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 13 14 15 16 17 18 19 20 21 22 23 24 display position ddram address fig.17 ddram-to-display mapping; left shift (pcf2114x). h andbook, full pagewidth 01 02 03 04 05 06 07 08 09 0a 0b 0c 1 23 4 5 67 8 9 10 11 12 mlb901 display position ddram address 0d 0e 0f 10 11 12 13 14 15 16 17 18 13 14 15 16 17 18 19 20 21 22 23 24 display position ddram address
1997 apr 07 22 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 8.18 programming mux 1 : 32 displays with the pcf2114x to drive a 2-line by 24 characters mux 1 : 32 display, use instruction function set m, n to 0, 1. note that the right half of the display needs mirrored column connection compared to a display driven by a pcf2116x. to drive a 4-line by 12 characters mux 1 : 32 display the pcf2116x operating instructions apply. there is no functional difference between the pcf2114x and the pcf2116x in this mode. for such an application set m, n to 1, 1 with the function set instruction. 8.19 reset function the pcf2116 automatically initializes (resets) when power is turned on. after reset the chip has the following state. table 2 state after reset step description 1 display clear 2 function set dl = 1 8-bit interface m, n = 0 1-line display g = 0 voltage generator; v lcd =v 0 3 display on/off control d = 0 display off c = 0 cursor off b = 0 blink off 4 entry mode set i/d = 1 +1 (increment) s = 0 no shift 5 default address pointer to ddram. the busy flag (bf) indicates the busy state (bf = logic 1) until initialization ends. the busy state lasts 2 ms. the chip may also be initialized by software. see figs 28 and 29. 6i 2 c-bus interface reset 9 instructions only two pcf2116 registers, the instruction register (ir) and the data register (dr) can be directly controlled by the microcontroller. before internal operation, control information is stored temporarily in these registers to allow interface to various types of microcontrollers which operate at different speeds or to allow interface to peripheral control ics. the pcf2116 operation is controlled by the instructions shown in table 3 together with their execution time. details are explained in subsequent sections. instructions are of 4 categories, those that: 1. designate pcf2116 functions such as display format, data length, etc. 2. set internal ram addresses 3. perform data transfer with internal ram 4. others. in normal use, category 3 instructions are used most frequently. however, automatic incrementing by 1 (or decrementing by 1) of internal ram addresses after each data write lessens the microcontroller program load. the display shift in particular can be performed concurrently with display data write, enabling the designer to develop systems in minimum time with maximum programming efficiency. during internal operation, no instruction other than read busy flag and address will be executed. because the busy flag is set to logic 1 while an instruction is being executed, check to make sure it is on logic 0 before sending the next instruction or wait for the maximum instruction execution time, as given in table 3. an instruction sent while the busy flag is high will not be executed.
1997 apr 07 23 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family table 3 instructions (note 1) notes 1. in the i 2 c-bus mode the dl bit is don't care. 8-bit mode is assumed. in the i 2 c-bus mode a control byte is required when rs or r/ w is changed; control byte: co, rs, r/ w, 0, 0, 0, 0, 0; command byte: db7 to db0. 2. example: f osc = 150 khz, = 6.67 m s; 3 cycles = 20 m s, 165 cycles = 1.1 ms. instruction rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 description required clock cycles (2) nop 0000000000no operation. 0 clear display 0000000001 clears entire display and sets ddram address 0 in address counter. 165 return home 0000000010 sets ddram address 0 in address counter. also returns shifted display to original position. ddram contents remain unchanged. 3 entry mode set 00000001i/ds sets cursor move direction and speci?es shift of display. these operations are performed during data write and read. 3 display control 0000001dcb sets entire display on/off (d), cursor on/off (c) and blink of cursor position character (b). 3 cursor/display shift 000001s/cr/l00 moves cursor and shifts display without changing ddram contents. 3 function set 00001dlnmg0 sets interface data length (dl), number of display lines (n, m) and voltage generator control (g). 3 set cgram address 0001 a cg sets cgram address. 3 set ddram address 001 a dd sets ddram address. 3 read busy ?ag and address 0 1 bf a c reads busy flag (bf) indicating internal operation is being performed and reads address counter contents. 0 read data 1 1 read data reads data from cgram or ddram. 3 write data 1 0 write data writes data to cgram or ddram. 3 t cy 1 f osc --------- =
1997 apr 07 24 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family table 4 command bit identities bit 0 1 i/d decrement increment s display freeze display shift d display off display on c cursor off cursor on b character at cursor position does not blink character at cursor position blinks s/c cursor move display shift r/l left shift right shift dl 4 bits 8 bits g voltage generator: v lcd =v 0 voltage generator; v lcd =v 0 - 0.8v dd n, (m = 0) pcf2116x 1 line 24 characters; mux 1 : 16 2 lines 24 characters; mux 1 : 32 pcf2114x 2 line 12 characters; mux 1 : 16 2 lines 24 characters; mux 1 : 32 n, (m = 1) reserved 4 lines 12 characters; mux 1 : 32 bf end of internal operation internal operation in progress co last control byte, only data bytes to follow next two bytes are a data byte and another control byte fig.18 4-bit transfer example. mga804 rs e db7 r/w db6 db5 db4 instruction write busy flag and address counter read data register read ir7 ir3 bf ac3 dr7 dr3 ir6 ir2 ac6 ac2 dr6 dr2 ir5 ir1 ac5 ac1 dr5 dr1 ir4 ir0 ac4 ac0 dr4 dr0
1997 apr 07 25 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family fig.19 an example of 4-bit data transfer timing sequence. mga805 rs e internal db7 r/w internal operation ir7 ir3 ac3 d7 d3 not busy ac3 busy instruction write busy flag check busy flag check instruction write ir7, ir3: instruction 7 th bit, 3 rd bit. ac3: address counter 3 rd bit. fig.20 example of busy flag check timing sequence. mga806 instruction write busy flag check busy flag check busy flag check instruction write internal operation rs e internal db7 r/w data busy busy not busy data
1997 apr 07 26 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 9.1 clear display clear display writes space code 20 (hexadecimal) into all ddram addresses (the character pattern for character code 20 must be blank pattern). sets the ddram address counter to logic 0. returns display to its original position if it was shifted. thus, the display disappears and the cursor or blink position goes to the left edge of the display (the first line if 2 or 4 lines are displayed). sets entry mode i/d = logic 1 (increment mode). s of entry mode does not change. the instruction clear display requires extra execution time. this may be allowed for by checking the busy-flag (bf) or by waiting until 2 ms has elapsed. the latter must be applied where no read-back options are foreseen, as in some chip-on-glass (cog) applications. 9.2 return home return home sets the ddram address counter to logic 0. returns display to its original position if it was shifted. ddram contents do not change. the cursor or blink position goes to the left of the display (the first line if 2 or 4 lines are displayed). i/d and s of entry mode do not change. 9.3 entry mode set 9.3.1 i/d when i/d = logic 1 (0) the ddram or cgram address increments (decrements) by 1 when data is written into or read from the ddram or cgram. the cursor or blink position moves to the right when incremented and to the left when decremented. the cursor and blink are inhibited when the cgram is accessed. 9.3.2 s when s = logic 1, the entire display shifts either to the right (i/d = logic 0) or to the left (i/d = logic 1) during a ddram write. thus it looks as if the cursor stands still and the display moves. the display does not shift when reading from the ddram, or when writing into or reading out of the cgram. when s = logic 0 the display does not shift. 9.4 display on/off control 9.4.1 d the display is on when d = logic 1 and off when d = logic 0. display data in the ddram are not affected and can be displayed immediately by setting d to logic 1. 9.4.2 c the cursor is displayed when c = logic 1 and inhibited when c = logic 0. even if the cursor disappears, the display functions i/d, etc. remain in operation during display data write. the cursor is displayed using 5 dots in the 8 th line (see fig.12). 9.4.3 b the character indicated by the cursor blinks when b = logic 1. the blink is displayed by switching between display characters and all dots on with a period of 1 second when f osc = 150 khz (see fig.12). at other clock frequencies the blink period is equal to 150 khz/f osc . the cursor and the blink can be set to display simultaneously. 9.5 cursor/display shift cursor/display shift moves the cursor position or the display to the right or left without writing or reading display data. this function is used to correct a character or move the cursor through the display. in 2 or 4-line displays, the cursor moves to the next line when it passes the last position (40 or 20 decimal) of the line. when the displayed data is shifted repeatedly all lines shift at the same time; displayed characters do not shift into the next line. the address counter (ac) content does not change if the only action performed is shift display, but increments or decrements with the cursor shift. 9.6 function set 9.6.1 dl ( parallel mode only ) defines interface data width when the parallel data interface is used. data is sent or received in bytes (bits db7 to db0) when dl = logic 1, or in two 4-bit nibbles (db7 to db4) when dl = logic 0. when 4-bit width is selected, data is transmitted in two cycles using the parallel bus (1) . when using the i 2 c-bus interface the dl should not previously have been set to 0 using the parallel interface. 9.6.2 n, m sets number of display lines. (1) in a 4-bit application db3 to db0 are left open (internal pull-ups). hence in the ?rst function set instruction after power-on, g and h are set to 1. a second function set must then be sent (2 nibbles) to set g and h to their required values.
1997 apr 07 27 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 9.6.3 g controls the v lcd voltage generator characteristic. 9.7 set cgram address set cgram address sets bit 0 to 5 of the cgram address (a cg in table 3) into the address counter (binary a[5] to a[0]). data can then be written to or read from the cgram. only bits 0 to 5 of the cgram address are set by the set cgram address instruction. bit 6 can be set using the set ddram address instruction or by using the auto-increment feature during cgram write. all bits 0 to 6 can be read using the read busy flag and address instruction. 9.8 set ddram address set ddram address sets the ddram address (a dd in table 3) into the address counter (binary a[6] to a[0]). data can then be written to or read from the ddram. hexadecimal address ranges. 9.9 read busy ?ag and address read busy flag and address reads the busy flag (bf). bf = logic 1 indicates that an internal operation is in progress. the next instruction will not be executed until bf = logic 0, so bf should be checked before sending another instruction. at the same time, the value of the address counter (a c in table 3) expressed in binary a[6] to a[0] is read out. the address counter is used by both cgram and ddram, and its value is determined by the previous instruction. 9.10 write data to cgram or ddram writes binary 8-bit data d[7] to d[0] to the cgram or the ddram. whether the cgram or ddram is to be written into is determined by the previous specification of cgram or ddram address setting. address function 00 to 4f 1-line by 24; 2114x/2116x 00 to 0b and 0c to 4f 2-line by 12; 2114x 00 to 27 and 40 to 67 2-line by 24; 2114x/2116x 00 to 13, 20 to 33, 40 to 53 and 60 to 73 4-line by 12; 2114x/2116x after writing, the address automatically increments or decrements by 1, in accordance with the entry mode. only bits d[4] to d[0] of cgram data are valid, bits d[7] to d[5] are dont care. 9.11 read data from cgram or ddram reads binary 8-bit data d[7] to d[0] from the cgram or ddram. the most recent set address instruction determines whether the cgram or ddram is to be read. the read data instruction gates the content of the data register (dr) to the bus while e = high. after e goes low again, internal operation increments (or decrements) the ac and stores ram data corresponding to the new ac into the dr. remark : the only three instructions that update the data register (dr) are: set cgram address set ddram address read data from cgram or ddram. other instructions (e.g. write data, cursor/display shift, clear display, return home) will not modify the data register content. 10 interface to microcontroller (parallel interface) the pcf2116 can send data in either two 4-bit operations or one 8-bit operation and can thus interface to 4-bit or 8-bit microcontrollers. in 8-bit mode data is transferred as 8-bit bytes using the 8 data lines db0 to db7. three further control lines e, rs, and r/ w are required. in 4-bit mode data is transferred in two cycles of 4-bits each. the higher order bits (corresponding to db4 to db7 in 8-bit mode) are sent in the first cycle and the lower order bits (db0 to db3 in 8-bit mode) in the second. data transfer is complete after two 4-bit data transfers. it should be noted that two cycles are also required for the busy flag check. 4-bit operation is selected by instruction. see figs 18, 19 and 20 for examples of bus protocol. in 4-bit mode pins db3 to db0 must be left open-circuit. they are pulled up to v dd internally.
1997 apr 07 28 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 11 interface to microcontroller (i 2 c-bus interface) 11.1 characteristics of the i 2 c-bus the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor. data transfer may be initiated only when the bus is not busy. 11.2 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. 11.3 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p). 11.4 system con?guration a device generating a message is a transmitter, a device receiving a message is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves. 11.5 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. each byte of eight bits is followed by an acknowledge bit. the acknowledge bit is a high level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. 11.6 i 2 c-bus protocol before any data is transmitted on the i 2 c-bus, the device which should respond is addressed first. the addressing is always carried out with the first byte transmitted after the start procedure. the i 2 c-bus configuration for the different pcf2116 read and write cycles is shown in figs 25 to 27.
1997 apr 07 29 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family fig.21 bit transfer. mbc621 data line stable; data valid change of data allowed sda scl fig.22 definition of start and stop conditions. mbc622 sda scl p stop condition sda scl s start condition
1997 apr 07 30 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family fig.23 system configuration. mga807 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver fig.24 acknowledgement on the i 2 c-bus. mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
1997 apr 07 31 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family u ll pagewidth s a 0 s 011101 0a slave address control byte a data a data a r/w 2n 0 bytes acknowledgement from pcf2116 control byte a mbh668 p update data pointer n 0 bytes 1 byte s a 0 011101 0 pcf2116 slave address r/w 1 co 0 co fig.25 master transmits to slave receiver; write mode.
1997 apr 07 32 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family handbook, full pagewidth s a 0 s 011101 0a slave address control byte a 1 co data a 1 1 control a r/w 0 co 2 bytes 2n 0 bytes data a acknowledgement from pcf2116 mga809 - 1 s a 0 s 1a data a 1 p slave address data acknowledgement from pcf2116 no acknowledgement from master r/w n bytes last byte update data pointer (1) fig.26 master reads after setting word address; write word address, set rs/ rw; read data. (1) last data byte is a dummy byte (may be omitted).
1997 apr 07 33 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family fig.27 master reads slave immediately after first byte; read mode (rs previously defined). h andbook, full pagewidth mga810 - 1 s a 0 s 1a data a 1 p slave address data acknowledgement from pcf2116 no acknowledgement from master r/w n bytes last byte update data pointer acknowledgement from master
1997 apr 07 34 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family handbook, full pagewidth mga811 - 1 t high t r t low t hd;sta t buf sda scl t f t/f scl t su;sto start condition (s) bit 7 msb (a7) bit 6 (a6) bit 0 lsb r/w acknowledge (a) stop condition (p) protocol fig.28 i 2 c-bus timing diagram; rise and fall times refer to v il and v ih .
1997 apr 07 35 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 12 limiting values in accordance with the absolute maximum rating system (iec 134). 13 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices (see handling mos devices ). symbol parameter min. max. unit v dd supply voltage - 0.5 +8.0 v v lcd lcd supply voltage v dd - 11 v dd v v i input voltage osc, v 0 , rs, r/ w, e and db0 to db7 v ss - 0.5 v dd + 0.5 v v o output voltage r1 to r32, c1 to c60 and v lcd v lcd - 0.5 v dd + 0.5 v i i dc input current - 10 +10 ma i o dc output current - 10 +10 ma i dd , i ss , i lcd v dd , v ss or v lcd current - 50 +50 ma p tot total power dissipation - 400 mw p o power dissipation per output - 100 mw t stg storage temperature - 65 +150 c
1997 apr 07 36 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 14 dc characteristics v dd = 2.5 to 6 v; v ss =0v; v lcd =v dd - 3.5 to v dd - 9 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v dd supply voltage 2.5 - 6.0 v v lcd lcd supply voltage v dd - 9 - v dd - 3.5 v i dd supply current external v lcd note 1 i dd1 supply current 1 - 200 500 m a i dd2 supply current 2 v dd =5v; v op =9v; f osc = 150 khz; t amb =25 c - 200 300 m a i dd3 supply current 3 v dd =3v; v op =5v; f osc = 150 khz; t amb =25 c - 150 200 m a i dd supply current internal v lcd notes 1, 2 and 8 i dd4 supply current 4 - 700 1100 m a i dd5 supply current 5 v dd =5v; v op =9v; f osc = 150 khz; t amb =25 c - 600 900 m a i dd6 supply current 6 v dd =3v; v op =5v; f osc = 150 khz; t amb =25 c - 500 800 m a i lcd v lcd input current notes 1 and 7 - 50 100 m a v por power-on reset voltage level note 3 - 1.3 1.8 v logic v il1 low level input voltage e, rs, r/ w, db0 to db7 and sa0 v ss - 0.3v dd v v ih1 high level input voltage e, rs, r/ w, db0 to db7 and sa0 0.7v dd - v dd v v il(osc) low level input voltage osc v ss - v dd - 1.5 v v ih(osc) high level input voltage osc v dd - 0.1 - v dd v v il(v0) low level input voltage v 0 v ss - v dd - 0.5 v v ih(v0) high level input voltage v 0 v dd - 0.05 - v dd v i pu pull-up current at db0 to db7 v i =v ss 0.04 0.15 1.00 m a i ol(db) low level output current db0 to db7 v ol = 0.4 v; v dd = 5 v 1.6 -- ma i oh(db) high level output current db0 to db7 v oh =4v; v dd =5v - 1.0 -- ma i l1 leakage current osc, v 0 , e, rs, r/ w, db0 to db7 and sa0 v i =v dd or v ss - 1 - +1 m a
1997 apr 07 37 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family notes 1. lcd outputs are open-circuit; inputs at v dd or v ss ; v 0 =v dd ; bus inactive; internal or external clock with duty cycle 50% (i dd1 only). 2. lcd outputs are open-circuit; lcd supply voltage generator is on; load current at v lcd =20 m a. 3. resets all logic when v dd 1997 apr 07 38 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 16 ac characteristics v dd = 2.5 to 6.0 v; v ss =0v; v lcd =v dd - 3.5vtov dd - 9 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. notes 1. v dd =5v. 2. all timing values are valid within the operating supply voltage and ambient temperature range and are referenced to v il and v ih with an input voltage swing of v ss to v dd . symbol parameter min. typ. max. unit f fr lcd frame frequency (internal clock); note 1 40 65 100 hz f osc external clock frequency 90 150 225 khz bus timing characteristics: parallel interface; notes 1 and 2 w rite operation ( writing data from microcontroller to pcf2116) t cy enable cycle time 500 -- ns pw eh enable pulse width 220 -- ns t asu address set-up time 50 -- ns t ah address hold time 25 -- ns t dsw data set-up time 60 -- ns t hd data hold time 25 -- ns r ead operation ( reading data from pcf2116 to microcontroller ) t cy enable cycle time 500 -- ns pw eh enable pulse width 220 -- ns t asu address set-up time 50 -- ns t ah address hold time 25 -- ns t dhd data delay time -- 150 ns t hd data hold time 20 - 100 ns timing characteristics: i 2 c-bus interface; note 2 f scl scl clock frequency -- 100 khz t sw tolerable spike width on bus -- 100 ns t buf bus free time 4.7 --m s t su;sta set-up time for a repeated start condition 4.7 --m s t hd;sta start condition hold time 4 --m s t low scl low time 4.7 --m s t high scl high time 4 --m s t r scl and sda rise time -- 1 m s t f scl and sda fall time -- 0.3 m s t su;dat data set-up time 250 -- ns t hd;dat data hold time 0 -- ns t su;sto set-up time for stop condition 4 --m s
1997 apr 07 39 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 17 timing characteristics fig.29 parallel bus write operation sequence; writing data from microcontroller to pcf2116. b ook, full pagewidth rs e db0 to db7 v v v v v v v v v v v v v t ih1 il1 ih1 il1 ih1 il1 il1 il1 ih1 il1 ih1 il1 v il1 v ih1 il1 cy t dsw h t eh pw t ah t ah t as valid data mla798 - 1 r/w fig.30 parallel bus read operation sequence; reading data from pcf2116 to microcontroller. d book, full pagewidth rs r/w e db0 to db7 v v v v v v v v v v ih1 il1 ih1 il1 ih1 il1 ih1 il1 v ol1 v oh1 il1 t cy dhr t eh pw t ah t ah t as ih1 v ol1 v oh1 t ddr v ih1 mla799 - 1
1997 apr 07 40 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 18 application information fig.31 direct connection to 8-bit microcontroller; 8-bit bus. handbook, 4 columns mga812 - 1 pcf2116 db0 to db7 e rs r/w 8 32 r1 to r32 c1 to c60 60 p20 p21 p22 p10 to p17 p80cl51 to lcd fig.32 direct connection to 8-bit microcontroller; 4-bit bus. handbook, 4 columns mga813 - 1 pcf2116 db4 to db7 e rs r/w 4 32 r1 to r32 c1 to c60 60 p10 p11 p12 p14 to p17 p80cl51 to lcd fig.33 typical application using parallel interface. handbook, full pagewidth mga816 - 1 v lcd v dd v o v ss pcf2116 v ss v dd 100 nf db0 to db7 e rs r/w 2 x 24 character lcd display (split screen) 16 c1 to c60 60 60 16 osc 100 nf 100 k w r7 to r16 r25 to r32 r1 to r8 r17 to r24
1997 apr 07 41 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family fig.34 application using i 2 c-bus interface. ha ndbook, full pagewidth v lcd v dd v o v ss pcf2116 v ss v dd 100 nf 2 x 24 character lcd display (split screen) 16 c1 to c60 60 60 16 osc 100 nf 100 k w 100 k w mga817 - 1 v lcd v dd v o v ss pcf2114 v ss v dd 100 nf 2 x 12 character lcd display 16 c1 to c60 60 osc 100 nf r1 to r16 r17 to r24 r1 to r16 sa0 sa0 v ss v dd v dd v dd scl sda master transmitter pcf84c81
1997 apr 07 42 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 18.1 8-bit operation, 1-line display using internal reset table 6 shows an example of a 1-line display in 8-bit operation. the pcf2116 functions must be set by the function set instruction prior to display. since the display data ram can store data for 80 characters, the ram can be used for advertising displays when combined with display shift operation. since the display shift operation changes display position only and ddram contents remain unchanged, display data entered first can be displayed when the return home operation is performed. 18.2 4-bit operation, 1-line display using internal reset the program must set functions prior to 4-bit operation. table 5 shows an example. when power is turned on, 8-bit operation is automatically selected and the pcf2116 attempts to perform the first write as an 8-bit operation. since nothing is connected to db0 to db3, a rewrite is then required. however, since one operation is completed in two accesses of 4-bit operation, a rewrite is required to set the functions (see table 5 step 3). thus, db4 to db7 of the function set are written twice. 18.3 8-bit operation, 2-line display for a 2-line display, the cursor automatically moves from the first to the second line after the 40 th digit of the first line has been written. thus, if there are only 8 characters in the first line, the ddram address must be set after the eighth character is completed (see table 7). note that both lines of the display are always shifted together; data does not shift from one line to the other. 18.4 i 2 c operation, 1-line display a control byte is required with most instructions (see table 8). 18.5 initializing by instruction if the power supply conditions for correctly operating the internal reset circuit are not met, the pcf2116 must be initialized by instruction. tables 9 and 10 show how this may be performed for 8-bit and 4-bit operation. table 5 4-bit operation, 1-line display example; using internal reset step instruction display operation 1 power supply on (pcf2116 is initialized by the internal reset circuit) initialized. no display appears. 2 function set rs r/ w db7 db6 db5 db4 sets to 4-bit operation. in this instance operation is handled as 8-bits by initialization and only this instruction completes with one write. 000010 3 function set 000010 sets to 4-bit operation, selects 1-line display and v lcd =v 0 . 4-bit operation starts from this point and resetting is needed. 000000 4 display on/off control 000000 _ turns on display and cursor. entire display is blank after initialization. 001110 5 entry mode set 000000 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the dd/cgram. display is not shifted. 000110 6 write data to cgram/ddram 100101 p_ writes p. the ddram has already been selected by initialization at power-on. the cursor is incremented by 1 and shifted to the right. 100000
1997 apr 07 43 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family table 6 8-bit operation, 1-line display example; using internal reset (character set a) step instruction display operation 1 power supply on (pcf2116 is initialized by the internal reset function) initialized. no display appears. 2 function set rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 sets to 8-bit operation, selects 1-line display and v lcd =v 0 . 0000110000 3 display mode on/off control 0000001110 _ turns on display and cursor. entire display is blank after initialization. 4 entry mode set 0000000110 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the dd/cgram. display is not shifted. 5 write data to cgram/ddram 1001010000 p_ writes p. the ddram has already been selected by initialization at power-on. the cursor is incremented by 1 and shifted to the right. 6 write data to cgram/ddram 1001001000 ph_ writes h. 7 | | | 8 write data to cgram/ddram 1001010011 philips_ writes s. 9 entry mode set 0000000111 philips_ sets mode for display shift at the time of write. 10 write data to cgram/ddram 1000100000 philips_ writes space. 11 write data to cgram/ddram 1001001101 philips m_ writes m.
1997 apr 07 44 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 12 | | | 13 write data to cgram/ddram 1001001111 microko writes o. 14 cursor or display shift 0000010000 microk o shifts only the cursor position to the left. 15 cursor or display shift 0000010000 micro ko shifts only the cursor position to the left. 16 write data to cgram/ddram 1001000011 icroc o writes c correction. the display moves to the left. 17 cursor or display shift 0000011100 microc o shifts the display and cursor to the right. z18 cursor or display shift 0000010100 microco_ shifts only the cursor to the right. 19 write data to cgram/ddram 1001001101 icrocom_ writes m. 20 | | | 21 return home 0000000010 philips m returns both display and cursor to the original position (address 0). step instruction display operation
1997 apr 07 45 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family table 7 8-bit operation, 2-line display example; using internal reset step instruction display operation 1 power supply on (pcf2116 is initialized by the internal reset function) initialized. no display appears. 2 function set sets to 8-bit operation, selects 2-line display and voltage generator off. rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 0000111000 3 display on/off control _ turns on display and cursor. entire display is blank after initialization. 0000001110 4 entry mode set _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the cg/ddram. display is not shifted. 0000000110 5 write data to cgram/ddram p_ writes p. the ddram has already been selected by initialization at power-on. the cursor is incremented by 1 and shifted to the right. w 1001010000 6 | | | 7 write data to cgram/ddram philips_ writes s. 1001010011 8 set ddram address philips sets ddram address to position the cursor at the head of the 2nd line. 0011000000 _ 9 write data to cgram/ ddram philips writes m. 1001001101 m_ 10 | | |
1997 apr 07 46 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 11 write data to cgram/ ddram philips writes o. 1001001111 microco_ 12 write data to cgram/ ddram philips sets mode for display shift at the time of write. 0000000111 microco_ 13 write data to cgram/ ddram philips writes m. display is shifted to the left. the ?rst and second lines shift together. 1001001101 icrocom_ 14 | | | 15 return home philips returns both display and cursor to the original position (address 0). 0000000010 microcom step instruction display operation
1997 apr 07 47 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family table 8 example of i 2 c operation; 1-line display (using internal reset, assuming sa0 = v ss ; note 1) step i 2 c byte display operation 1i 2 c start initialized. no display appears. 2 slave address for write sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/ w ack during the acknowledge cycle sda will be pulled-down by the pcf2116. 011101001 3 send a control byte for function set co rs r/ w ack control byte sets rs and r/ w for following data bytes. 0 0 0xxxxx1 4 function set db7 db6 db5 db4 db3 db2 db1 db0 ack selects 1-line display and v lcd =v 0 ; scl pulse during acknowledge cycle starts execution of instruction. 001x00001 5 display on/off control _ db7 db6 db5 db4 db3 db2 db1 db0 ack turns on display and cursor. entire display shows character hex 20 (blank in ascii-like character sets). 000011101 6 entry mode set _ db7 db6 db5 db4 db3 db2 db1 db0 ack sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the ddram or cgram. display is not shifted. 000001101 7i 2 c start _ for writing data to ddram, rs must be set to 1. therefore a control byte is needed. 8 slave address for write _ sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/ w ack 011101001 9 send a control byte for write data _ co rs r/ w ack 0 1 0xxxxx1 10 write data to ddram db7 db6 db5 db4 db3 db2 db1 db0 ack writes p. the ddram has been selected at power-up. the cursor is incremented by 1 and shifted to the right. 010100001 p_
1997 apr 07 48 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 11 write data to ddram ph_ db7 db6 db5 db4 db3 db2 db1 db0 ack writes h. 010010001 12 to 15 | | | | 16 write data to ddram philips_ db7 db6 db5 db4 db3 db2 db1 db0 ack writes s. 010100111 17 (optional i 2 c stop) i 2 c start + slave address for write (as step 8) philips_ 18 control byte philips_ co rs r/ w ack 1 0 0xxxxx1 19 return home db7 db6 db5 db4 db3 db2 db1 db0 ack sets ddram address 0 in address counter. (also returns shifted display to original position. ddram contents unchanged). this instruction does not update the data register 000000101 philips 20 control byte for read co rs r/ w ack ddram content will be read from following instructions. the r/ w has to be set to 1 while still in i 2 c-write mode. 0 1 1xxxxx1 philips 21 i 2 c start philips 22 slave address for read sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/ w ack during the acknowledge cycle the content of the dr is loaded into the internal i 2 c interface to be shifted out. in the previous instruction neither a set address nor a read data has been performed. therefore the content of the dr was unknown. 011101011 p hilips 23 read data: 8 scl + master acknowledge; note 2 db7 db6 db5 db4 db3 db2 db1 db0 ack 8 scl; content loaded into interface during previous acknowledge cycle is shifted out over sda. msb is db7. during master acknowledge content of ddram address 01 is loaded into the i 2 c interface. xxxxxxxx0 ph ilips step i 2 c byte display operation
1997 apr 07 49 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family notes 1. x = dont care. 2. sda is left at high-impedance by the microcontroller during the read acknowledge. 24 read data: 8 scl + master acknowledge; note 2 db7 db6 db5 db4 db3 db2 db1 db0 ack 8 scl; code of letter h is read ?rst. during master acknowledge code of i is loaded into the i 2 c interface. 010010000 philips 25 read data: 8 scl + no master acknowledge; note 2 db7 db6 db5 db4 db3 db2 db1 db0 ack no master acknowledge; after the content of the i 2 c interface register is shifted out no internal action is performed. no new data is loaded to the interface register, data register (dr) is not updated, address counter (ac) is not incremented and cursor is not shifted. 010010011 phi lips 26 i 2 c stop phi lips step i 2 c byte display operation
1997 apr 07 50 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family table 9 initialization by instruction, 8-bit interface (note 1) note 1. x = dont care. step description power-on or unknown state | wait 2 ms after v dd rises above v por | rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 bf cannot be checked before this instruction. 0 0 0 0 1 1 x x x x function set (interface is 8-bits long). | wait 2 ms | rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 bf cannot be checked before this instruction. 0 0 0 0 1 1 x x x x function set (interface is 8-bits long). | wait more than 40 m s | rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 bf cannot be checked before this instruction. 0 0 0 0 1 1 x x x x function set (interface is 8-bits long). | | bf can be checked after the following instructions. when bf is not checked, the waiting time between instructions is the speci?ed instruction time (see table 3). rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 function set (interface is 8-bits long). specify the number of display lines and voltage generator characteristic. 000011nmg0 0 0 0 0 0 0 1 0 0 0 display off. 0 0 0 0 0 0 0 0 0 1 clear display. 0 0 0 0 0 0 0 1 i/d s entry mode set. | initialization ends
1997 apr 07 51 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family table 10 initialization by instruction, 4-bit interface. not applicable for i 2 c-bus operation step description power-on or unknown state | wait 2 ms after v dd rises above v por | rs r/ w db7 db6 db5 db4 bf cannot be checked before this instruction. 000011 function set (interface is 8-bits long). | wait 2 ms | rs r/ w db7 db6 db5 db4 bf cannot be checked before this instruction. 000011 function set (interface is 8-bits long). | wait 40 m s | rs r/ w db7 db6 db5 db4 bf cannot be checked before this instruction. 000011 function set (interface is 8-bits long). | bf can be checked after the following instructions. when bf is not checked, the waiting time between instructions is the speci?ed instruction time. (see table 3). rs r/ w db7 db6 db5 db4 function set (set interface to 4-bits long). 000010 interface is 8-bits long. 000010 function set (interface is 4-bits long). 0 0 n m g 0 specify number of display lines and voltage generator characteristic. 000000 001000 display off. 000000 clear display. 000001 000000 entry mode set. 0 0 0 1 i/d s | initialization ends
1997 apr 07 52 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family fig.35 example of 2 24 display layout (pcf2116x). handbook, full pagewidth 1 316191120 c1 15 31 45 45 31 15 1 c16 30 46 60 60 46 30 16 r8 to r1 r9 to r16 r32 to r25 r17 to r24 pcf2116 column output numbers pcf2116 column output numbers lcd column numbers display layout: rows display layout: columns 2 x 24 character display mga814 - 1
1997 apr 07 53 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family fig.36 example of 4 12 display layout (pcf2114x/pcf2116x). handbook, full pagewidth c1 15 46 60 c16 45 r8 to r1 r9 to r16 r32 to r25 r17 to r24 display layout: rows display layout: columns pcf2116 column output numbers pcf2116 column output numbers lcd column numbers mga815 - 2 13160 dot matrix lcd
1997 apr 07 54 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family fig.37 display example (pcf2114x); 1-line by 24 characters. bo ok, full pagewidth 1 to 8 16 to 9 mlb897 display glass dot matrix column layout row layout 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 1 line by 24 characters display
1997 apr 07 55 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family b ook, full pagewidth 1 to 8 16 to 9 mlb898 display glass dot matrix column layout row layout 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2 lines by 12 characters display fig.38 display example (pcf2114x); 2-lines by 12 characters.
1997 apr 07 56 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family fig.39 chip on glass application. handbook, full pagewidth mga818 - 1 pcf2116 chip-on-glass 4 line by 12 character r1 r8 r17 r24 r9 r16 r25 r32 2116 c1 r9 c60 scl sda v lcd dd v v ss v 0
1997 apr 07 57 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 19 bonding pad locations handbook, full pagewidth mlb969 ? 6.99 mm ? 5.64 mm x pcf2114 pcf2116 y 0 0 c1 r24 r23 r22 r21 r20 r19 r18 r17 r8 r7 r6 r5 r4 r3 r2 r1 c31 c32 c30 c33 c34 c35 c36 c37 c38 c39 c21 c22 c23 c24 c25 c26 c27 c28 c29 c16 c17 c18 c19 c20 c7 c8 c9 c10 c11 c12 c13 c14 c15 c2 c3 c4 c5 c6 sa0 e ss1 r/w t1 ss2 rs osc db1 dd2 db0 dd1 r25 r26 r27 r28 r29 r30 r31 r16 r10 r11 r12 r13 r14 r15 r9 c40 c41 c42 c43 c44 c45 c47 c48 c46 c49 c50 c51 c52 c53 c54 c55 c56 c57 c58 c59 c60 r32 db7 scl db6 sda db5 0 lcd1 db4 lcd2 db3 lcd3 db2 v v v v v v v v fig.40 bonding pad locations. chip dimensions: approximately 5.64 6.99 mm. pad area: 0.0121 mm 2 . bonding pad dimensions: 110 110 m m.
1997 apr 07 58 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family table 11 bonding pad locations (dimensions in m m) all x/y coordinates are referenced to centre of chip, see fig.40. symbol pad x y osc 1 - 2445 - 3300 db1 2 - 2211 - 3300 v dd2 3 - 2034 - 3300 db0 4 - 1806 - 3300 v dd1 5 - 1627 - 3300 sa0 6 - 1437 - 3300 e7 - 1245 - 3300 v ss1 8 - 1056 - 3300 r/ w9 - 867 - 3300 t1 10 - 672 - 3300 v ss2 11 - 486 - 3300 rs 12 - 297 - 3300 r9 13 77 - 3300 r10 14 247 - 3300 r11 15 417 - 3300 r12 16 587 - 3300 r13 17 757 - 3300 r14 18 927 - 3300 r15 19 1097 - 3300 r16 20 1267 - 3300 r25 21 1436 - 3300 r26 22 1606 - 3300 r27 23 1776 - 3300 r28 24 1946 - 3300 r29 25 2116 - 3300 r30 26 2286 - 3300 r31 27 2456 - 3300 r32 28 2626 - 3013 c60 29 2626 - 2760 c59 30 2626 - 2590 c58 31 2626 - 2420 c57 32 2626 - 2250 c56 33 2626 - 2080 c55 34 2626 - 1910 c54 35 2626 - 1740 c53 36 2626 - 1570 c52 37 2626 - 1400 c51 38 2626 - 1230 c50 39 2626 - 1060 c49 40 2626 - 890 c48 41 2626 - 720 c47 42 2626 - 550 c46 43 2626 - 380 c45 44 2626 582 c44 45 2626 752 c43 46 2626 922 c42 47 2626 1092 c41 48 2626 1262 c40 49 2626 1432 c39 50 2626 1602 c38 51 2626 1772 c37 52 2626 1942 c36 53 2626 2112 c35 54 2626 2282 c34 55 2626 2452 c33 56 2626 2622 c32 57 2626 2792 c31 58 2626 2962 c30 59 2626 3132 c29 60 2339 3302 c28 61 2169 3302 c27 62 1999 3302 c26 63 1829 3302 c25 64 1659 3302 c24 65 1489 3302 c23 66 1319 3302 c22 67 1149 3302 c21 68 979 3302 c20 69 809 3302 c19 70 639 3302 c18 71 469 3302 c17 72 299 3302 c16 73 129 3302 c15 74 - 245 3302 c14 75 - 415 3302 c13 76 - 585 3302 symbol pad x y
1997 apr 07 59 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family c12 77 - 755 3302 c11 78 - 925 3302 c10 79 - 1095 3302 c9 80 - 1265 3302 c8 81 - 1435 3302 c7 82 - 1605 3302 c6 83 - 1775 3302 c5 84 - 1945 3302 c4 85 - 2115 3302 c3 86 - 2285 3302 c2 87 - 2455 3302 c1 88 - 2625 3015 r24 89 - 2625 2846 r23 90 - 2625 2676 r22 91 - 2625 2506 r21 92 - 2625 2336 r20 93 - 2625 2166 r19 94 - 2625 1996 r18 95 - 2625 1826 r17 96 - 2625 1656 r8 97 - 2625 1487 r7 98 - 2625 1317 r6 99 - 2625 1147 r5 100 - 2625 977 r4 101 - 2625 807 r3 102 - 2625 637 r2 103 - 2625 467 r1 104 - 2625 297 db7 105 - 2625 - 290 scl 106 - 2625 - 479 db6 107 - 2625 - 716 sda 108 - 2625 - 976 db5 109 - 2625 - 1202 v 0 110 - 2625 - 1388 v lcd1 111 - 2625 - 1580 db4 112 - 2625 - 1808 v lcd2 113 - 2625 - 1985 db3 114 - 2625 - 2213 v lcd3 115 - 2625 - 2390 db2 116 - 2625 - 2621 symbol pad x y
1997 apr 07 60 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 20 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.15 15.85 0.70 0.58 0.81 0.59 7 0 o o 0.12 0.2 0.1 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot425-1 96-04-02 d (1) (1) (1) 20.1 19.9 h d 22.15 21.85 e z 0.81 0.59 d 0 5 10 mm scale b p e q e a 1 a l p q detail x l (a ) 3 b c b p e h a 2 d h v m b d z d a z e e v m a x 102 103 y w m w m a max. 1.6 lqfp128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm sot425-1 65 64 38 39 1 128 pin 1 index
1997 apr 07 61 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 21 soldering 21.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 21.2 re?ow soldering reflow soldering techniques are suitable for all lqfp packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. 21.3 wave soldering wave soldering is not recommended for lqfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering lqfp packages lqfp48 (sot313-2), lqfp64 (sot314-2) or lqfp80 (sot315-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 21.4 repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1997 apr 07 62 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family 22 definitions 23 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 24 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1997 apr 07 63 philips semiconductors product speci?cation lcd controller/drivers pcf2116 family notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca54 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - sp, brazil, tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, mumbai 400 018, tel. +91 22 4938 541, fax. +91 22 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 417067/1200/04/pp64 date of release: 1997 apr 07 document order number: 9397 750 01754

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